1. Field of the Invention
The invention relates to a semiconductor device and a method of automatically inspecting an appearance of a semiconductor device, particularly, a method of automatically inspecting an appearance for removing a WLP (Wafer Level chip size Package) Flip Chip with a chipping occurring in the interlayer insulation film or the semiconductor substrate from an end portion of the WLP Flip Chip toward the element forming region.
2. Description of the Related Art
As a semiconductor device to set in electronics, a semiconductor device having equivalent size to the semiconductor element set therein, called CSP, is employed, that satisfies demands for miniaturization, thinner thickness and lighter weight for use in a mobile data device such as a mobile phone. A WLP Flip Chip is particularly miniaturized one of CSP. FIG. 5 is an enlarged view of a portion of a scribe region 18b and an element foaming region 18a adjacent thereto in a semiconductor wafer 70 before a wafer is diced into WLP Flip Chips.
Although the details of reference numerals in FIG. 5 will be described below, multiple layers of a plurality of interlayer insulation films 4 etc and metal wiring layers 7 etc as well as a device element (not shown) etc are formed in the element forming region 18a, and a TEG wiring layer 41 etc, a plurality of interlayer insulation films 4 etc, and a device element (not shown) etc forming a TEG (Test Element Group) region 15 are formed in the scribe region 18b. The plurality of interlayer insulation films 4 etc in the element forming region 18a and the plurality of interlayer insulation films 4 etc in the scribe region 18b are connected.
However, since a passivation film 5 formed of a silicon nitride film etc is hard and fragile, stress by a dicing process easily causes a crack in the passivation film 5 in the scribe region 18b. Therefore, as shown in FIG. 5, in order to prevent a crack in the passivation film 5 in the scribe region 18b from extending to the passivation film 5 in the element forming region 18a, the passivation films 5 in both the regions are isolated by providing a passivation film removed groove 21 in the scribe region 18b. A first resin layer 6 extends from on a portion of the passivation film removed groove 21 onto the element foaming region 18a so as to cover these.
In this state, when the wafer is diced along a scribe line 19 as a center line into the WLP Flip Chips, chippings of various sizes may occur in the interlayer insulation film 4 etc or a semiconductor substrate 1 in an end portion of the diced WLP Flip Chip. When these chippings extend to the interlayer insulation film 4 etc or the semiconductor substrate 1 under the first resin layer 6 in the end portion of the WLP Flip Chip, these chippings may cause a crack in the interlayer insulation film 4 etc or the semiconductor substrate 1, and the crack may extend to inside the element forming region 18a. When a crack occurs in the interlayer insulation film 4 etc or the semiconductor substrate 1 in the element forming region 18a, the device characteristics of the WLP Flip Chip may decrease, causing a problem in the yield and reliability.
Therefore, WLP Flip Chips separated by dicing undergo an appearance inspection process and chips having a chipping of predetermined size or more etc are removed so as to minimize the problem in the yield and reliability. FIG. 6A shows a schematic plan view of a WLP Flip Chip 30 separated by dicing the semiconductor wafer 70 shown in FIG. 5.
The end portion 32 of the first resin layer 6 shown in FIG. 5 is shown inside the chip end portion 31 of the WLP Flip Chip 30. The first resin layer 6 extends from the end portion 32 and covers the surface of the WLP Flip Chip 30. A guard ring 17 shown in FIG. 5 is disposed inside the end portion 32 of the first resin layer 6, being covered with the first resin layer 6 as shown by a dotted line. The end portion 32 of the first resin layer 6 extends to the passivation film removed groove 21 outside a guard ring end portion 17a. 
FIG. 6B is a plan view of the chip end portion 31 of the WLP Flip Chip 30 and the vicinity, showing a large chipping 34 occurring from the chip end portion 31 in the interlayer insulation film 4 etc, which is recognized as an appearance defective product by an appearance inspection. The appearance inspection is performed automatically by an automatic appearance inspection machine so as to reduce manpower. A chip of which a chipping end portion 34a extends to inside a judgment line 33 is judged as an appearance defective product. FIG. 6B also schematically shows the position of the scribe line 19 that is the center line of the dicing. The dicing is performed along the scribe line 19 as the center line, keeping a predetermined vertical width.
In principle, a chip is allowable as long as the chipping 34 has such size as not to extend to inside the end portion 32 of the first resin layer 6, and thus a non-defective or defective judgment is achieved by judging whether or not the chipping end portion 34a is in contact with the end portion 32 of the first resin layer 6. However, since the first resin layer 6 is formed by coating a liquid material such as polyimide, a resin easily flows and easily extends to the scribe line side, and the edge is often obscure.
For such a reason etc, when the end portion 32 of the first resin layer 6 is recognized by the automatic appearance inspection machine, the recognition accuracy varies largely. Therefore, the position of the unstable end portion 32 of the first resin layer 6 is not used for a non-defective/defective judgment by an appearance inspection. Instead, in order to avoid failing to find a defective product by an appearance inspection, the judgment line 33 is set in a position away from the end portion 32 of the first resin layer 6 recognized by the appearance inspection machine toward the chip end portion 31 by a predetermined value a, thereby making a non-defective or defective judgment by an appearance inspection. The judgment line 33 is set in a position away from the end portion 32 of the first resin layer 6 by about several μm.
FIG. 6C is an enlarged plan view of the chip end portion 31 of the WLP Flip Chip 30 and the vicinity, that is judged as a non-defective product by the appearance inspection machine. The end portion 34a of the chipping 34 lies in a position closer to the chip end portion 31 outside the judgment line 33. Therefore, the chipping 34 does not cause a crack extending to the element forming region 18a shown in FIG. 5 in the interlayer insulation film 4 etc.
In Japanese Patent Application publication No. 2011-014605, as shown in FIG. 7, in order to avoid connection between a plurality of interlayer insulation films 4 etc in an element forming region 18a and a plurality of interlayer insulation films 4 etc in a scribe region 18b, an insulation film removed groove 21a is provided in the scribe region 18b, in which an insulation film does not exist and a semiconductor substrate 1 is exposed. With this insulation film removed groove 21a, when a semiconductor wafer 80 is separated into individual WLP Flip Chips by dicing, a chipping 34 or a crack does not occur in the interlayer insulation film 4 etc from the chip end portion 31 toward the element forming region 18a. 
In detail, Japanese Patent Application publication No. 2011-14605 discloses preventing a crack in the interlayer insulation film 4 etc in the element forming region 18a due to a chipping 34 occurring in the interlayer insulation film 4 etc in the chip end portion 31. However, a chipping 34 occurs in the semiconductor substrate 1, and thus it is necessary to remove a chipping 34 having predetermined size or more by an appearance inspection machine as described above. It is noted that the same reference numerals among FIG. 5, FIG. 6 and FIG. 7 etc show the same components.
By the automatic appearance inspection of the WLP Flip Chip 30 described above, even when the end portion 32 of the first resin layer 6 is not in contact with the end portion 34a of the chipping 34 extending from the chip end portion 31 and does not have a practical problem, there is a case where the WLP Flip Chip 30 is judged as a defective product. This will be described referring to FIG. 6D.
When a pattern is formed in the first resin layer 6 after the first resin layer 6 made of polyimide etc is coated on the semiconductor wafer, an exposure machine having low mask alignment accuracy is often used without a mask alignment machine having high accuracy such as a stepper. This is to decrease the manufacturing cost since the pattern of the first resin layer 6 is not miniaturized one.
Therefore, there is a case where the amount of a mask misalignment is several μm or more, and the first resin layer 6 may be formed with the end portion 32 largely shifted toward the chip end portion 31 as shown in FIG. 6D. The amount of a mask misalignment in this case is apparent by comparing this with the position of the end portion 32 of the first resin layer 6 in FIG. 6C. As a result, the judgment line 33 crosses the chipping 34 and the WLP Flip Chip 30 is judged as an appearance defective product, thereby decreasing the yield in the appearance inspection process.
However, the end portion 34a of the chipping 34 is still not in contact with the end portion 32 of the first resin layer 6, and thus the chipping 34 does not cause a crack etc in the interlayer insulation film 4 etc in the element forming region 18a. Nevertheless, the WLP Flip Chip 30 is disposed of. This case occurs by determining the judgment line 33 by referencing the position of the unstable end portion 32 of the first resin layer 6. A similar case also occurs in FIG. 7.
In order to prevent such unnecessary decrease in the yield, it is essential to employ a stable reference line that is less influenced by a mask misalignment instead of using the position of the unstable end portion 32 of the first resin layer 6 as a judgment reference line for an automatic appearance inspection.